In recent years, as regards microprocessors constructed of semiconductor devices, especially of N-MOS (N-channel metal-oxide-semiconductor) transistors, it has become possible owing to the rapid progress of the semiconductor processing technology to produce such microprocessors which have high performance in spite of being at high densities of integration.
Owing to the high integration, the reliability of the processor is being enhanced with a decrease in the number of components. However, when a main memory is also taken into consideration, various factors for causing errors still exist.
Whether the error factor is attributed to hardware or to software, it is necessary to find out the factor as fast as possible and to return the processor to normalcy.
Especially in a processor used for control purposes, an error brings about a malfunction of the associated system which leads to system-down time. It is therefore an important matter to endow the processor with an RAS (reliability, availability, serviceability) function. In such uses, accordingly, the RAS function cannot be ignored even in the case of a microprocessor.
Heretofore, microprocessors have been employed for small-scale systems and often used in places where their malfunctions do not lead to any serious accident. Therefore, the error detecting function and the error processing function have been often omitted.
However, as microprocessors have had the performances and functions enhanced, some have reached the point of not being inferior to minicomputers in terms of performances and functions, and a RAS function to the same extent as in the minicomputer has been urgently needed for such microprocessors.
On account of various limitations of microprocessors, such as limitations in the architecture, limitations in the package (number of pins), and limitations in the density of integration, it has heretofore been difficult to assemble the error detecting function and the error processing function into an LSI (large scale integration) of a microprocessor and therefore such arrangements have generally not be constructed.
Instead, it has hitherto been common to cope with error processing by an LSI external circuit. The external circuit has accordingly increased the overall circuit size to make the scale of the whole processor large, which has been a most serious disadvantage.
This invention relates to an LSI microprocessor comprising an instruction fetch portion and an instruction execute portion which fetch and execute instructions are independent of each other under a microprogram control and which are subjected to a pipeline control while being synchronized.
Here, the "LSI microprocessor" has the instruction fetch portion and the instruction execute portion made up of one or two LSI chips. In this specification, for the sake of convenience of the description, the expression shall indicate a processor wherein each of the instruction fetch portion and the instruction execute portion is constructed of one LSI chip.